Continuous downscaling of semiconductor devices brings more and more challenges to semiconductor fabrication processes. For technology node below 14 nm, one of the most critical steps is a spacer etching. It requires a perfect anisotropy etching (no critical dimension (CD) loss) without damaging nor consumption of an exposed material like silicon, and silicon oxide. It is usually done by plasma etching using a fluorocarbon-based chemistry. However, with increased aspect ratios associated with advanced technology nodes, conventional etching processes no longer allow etch specifications, such as profile control (e.g., footing and surface roughness), damage-free to an underlying layer, CD control, etc., to be reached.
In industry, the standard etch process used for SiN etching is a HFC combined with oxidizer and/or noble gas, for example, CH3F combined with an oxidizer (e.g. O2), a noble gas (e.g. Ar or He), and occasionally an additional F or H containing gas (e.g. CH4, or CF4). However, it is difficult to manage tradeoffs between etch selectivity, profile control and damages to the underlying layer. Previous patents about SiN etch claimed using different HFCs to selectively etch SiN spacer but no quantifiable information regarding the profile control.
US20130105916A1 to Chang et al. discloses a high selectivity nitride etch process, which includes an anisotropic etching of SiN using HFC plasma to form HFC polymers on SiNx, SiO2, and Si of varying thicknesses. The process is a selective etching of SiN using a HFC having a formula CxHyFz where x=3-6, y>z, saturated or unsaturated, linear or cyclic. But Chang et al. do not disclose any discussion about profile control, such as footing control. The etch process Chang et al. disclose is not a cyclic process.
US20110068086A1 to Suzuki et al. disclose a plasma etching method on planar wafers including plasma etching a target using CxHyFz, x=3-5, y>z, saturated molecules only, linear or cyclic HFC. More specifically, Suzuki et al. discloses selectively etching of SiNx to SiO2 by utilizing the specific HFC under the plasma conditions on planar wafers rather than a patterned wafer containing semiconductor structures. As illustrated in the Example, Suzuki et al. used 2,2-Difluoro-n-butane to etch SiN planar wafer and SiO planar wafer.
U.S. Pat. No. 8,501,630 or US 20120077347A1 to Metz et al. discloses a plasma etching method for selectively etching a substrate. The plasma etching process uses a process composition having a process gas containing C, H and F, and a non-oxygen-containing additive gas. The process gas includes CH3F, CHF3, CH2F2, or any combination of two or more thereof. The plasma etching process that Metz et al. disclosed is not a cyclic process.
US 20010005634 A1 to Kajiwara discloses a dry etching method for forming a contact hole by high selective etching SiN over SiO2 using CH2F2 as an etching gas.
US20130105996 to Brink et al. discloses a low energy etch process for nitrogen-containing dielectric layer included in a stack that includes from bottom to top a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer formed on a substrate. The nitrogen-containing dielectric layer were plasma etched using HFC having CxHyFz, x=3-6, y>z. Brink et al. keep salient on selectivity to Si or SiO2.
US 20140273292A1 to Posseme et al. discloses methods of forming SiN spacers including the steps of depositing a SiN layer atop an exposed silicon containing layer and an at least partially formed gate stack disposed atop a substrate; modifying a portion of the SiN layer by exposing the SiN layer to a hydrogen or helium containing plasma that is substantially free of fluorine; and removing the modified portion of the SiN layer by performing a wet cleaning process to form the SiN spacers. In one embodiment, Posseme et al. discloses the SiN layer was etched using a HFC-containing gas such as CH2F2, CH4, CHF3.
US 20150270140A1 to Gupta et al. discloses atomic layer or cyclic plasma etching chemistries and processes to etch films including Si, Ti, Ta, W, Al, Pd, Ir, Co, Fe, B, Cu, Ni, Pt, Ru, Mn, Mg, Cr, Au, alloys thereof, oxides thereof, nitrides thereof, and combinations thereof. Examples include Fe and Pd etch using Cl2 and ethanol (EtOH), Ni, Co, Pd, or Fe etch using Cl2 and acetylacetonate (Acac).
US20160293438A1 to Zhou et al. discloses a cyclic spacer etching process with improved profile control, but the method is based on NF3/NH3 plasma, rather than HFC gases.
WO2018/044713 A1 to Sherpa et al. discloses a method of quasi-atomic layer etching of SiN including the first step of process gas containing H and optionally a noble gas; H2, or H2 and Ar; the second step: process gas containing N, F, O, and optionally a noble element NF3, O2, and Ar.
U.S. Pat. No. 9,318,343B2 to Ranjan et al. discloses a method to improve etch selectivity during SiN spacer etch that includes a cyclical process of etching and oxidation of a SiN spacer and silicon (such as polycrystalline silicon) using a process gas containing a HFC gas expressed as CxHyFz, wherein x, y, and z are non-zero. The HFC disclosed in Renjan et al, is CH3F. Ranjan et al. are silent about the profile of the spacers, such as footing and surface roughness of the spacers.
Discovery of new and novel etching components that are applicable to improving profile control for etching silicon-containing spacers, such as SiN spacer, is challenging, since their applications to etching the silicon-containing spacers have to meet the requirements of the etching profile, such as less to no footing, less to no fluoride formation, a smooth spacer surface after etching, etc. Thus, there are needs to provide such etching components to meet these requirements.